Interest in the use of SystemVerilog for verification is strong. Not surprisingly, many organizations that have lead the evolution in verification by using the proprietary HVL e, are exploring a move to standards and SystemVerilog. SystemVerilog is the recently ratified hardware description and verification language (HDVL) standard—a major extension of the established IEEE 1364-2001 Verilog language. This seminar provides guidance on transitioning to SystemVerilog for verification by showing and contrasting language capabilities and how common verification structures and techniques are implemented in both languages. This seminar will be particularly valuable to those using Verisity®’s e language.

		Introduction A summary of the development of the SystemVerilog language is presented as well as a refresher of the verification process. An overview of state-of-the-art techniques, including constrained-random stimulus, assertions, functional coverage and transaction-level verification is presented.
		SystemVerilog Basics The language features of particular relevance to a verification environment are introduced. A discussion of the SystemVerilog type system is presented and features which enhance strong-typing are introduced. Advanced data types of use in a verification environment such as dynamic and associative arrays, queues and structs are covered.
		Randomization and Constraints This section forms the heart of a constrained-random test automation environment. The key features required to implement such an environment are covered. Randomization, methods for controlling randomization and random case statements are presented. Random sequences are also introduced.
		Abstraction and Reuse The uses of the objected-oriented features of the language to implement abstract and reusable enviroments are presented. Such concepts as classes, inheritance, a comparison of object-oriented and aspect-oriented programming, and the techniques required to leverage these capabilities to improve reuse are covered.
		Functional Coverage A constrained-random environment requires functional coverage to provide the essential feedback on what was stimulated. The key constructs required to use functional coverage are introduced and the means to use these determine "when verification is complete".
		Communication and Scoreboarding These are the constructs required to create a reusable self-checking test environment which interfaces properly with the device-under-test (DUT). Such concepts as mailboxes, semaphores, events and the architecture of a scoreboard are discussed.
		Assertions Key SystemVerilog features which implement data and temporal checks are introduced in the context of assertion-based verification.
		Verification Environment This section puts all of the pieces together and demonstrates how to build a state-of-the-art test environment using the features of SystemVerilog. The interface between the testbench and design is covered as well as a presentation of a generic template for a reusable test environment.
		Using Testbenches and the Conclusion The conclusion provides information on using SystemVerilog to verify designs written in other language such as VHDL, Verilog, SystemC™. A summary of the verification features of SystemVerilog, such as its standards compliance and many rich features is presented.